Semiconductor device
US6335901B1 · kind B1 · utility
37Cited by
4References
38Claims
0Family size
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Key dates
| Filing date | Mar 20, 2000 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Mar 20, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4076
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An SDRAM has its operation mode selected to be the SDR mode in response to the first state of the external terminal (OPT), thereby releasing data, which has been read out of a memory mat, in response to a clock signal produced by a clock regenerating circuit having a function of comparing the phases of the input and output of the circuit, or selected to be the DDR mode in response to the second state of the external terminal (OPT), thereby releasing data, which has been read out of the memory mat, in response to a clock signal produced by a clock signal generation circuit in synchronism with an external clock signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.