High performance self balancing low cost network switching architecture based on distributed hierarchical shared memory
US6335932B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 30, 1999 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99945
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A data switch for network communications includes at least one first data port interface which supports a plurality of data ports which transmit and receive data at a first data rate. At least one second data port interface is provided; the at least one second data port interface supports a plurality of data ports transmitting and receiving data at a second data rate. A CPU interface is provided, with the CPU interface configured to communicate with a CPU. An internal memory is provided, and communicates with the at least one first data port interface and the at least one second data port interface. A memory management unit is provided, and includes an external memory interface for communicating data from at least one of the first data port interface and the second data port interface and an external memory. A communication channel is provided, with the communication channel communicating data and messaging information between the at least one first data port interface, the at least one second data port interface, the internal memory, and the memory management unit. The memory management unit directs data from one of the first data port and the second data port to one of the intern…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.