Memory based I/O decode arrangement, and system and method using the same
US6336158B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 30, 1998 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Oct 30, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/385
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An input/output (I/O) decode arrangement including an I/O decode map in a form of a memory block and containing, before start of any bus I/O transactions, I/O address decode information useable for I/O address decoding for bus transaction ownership, for at least a portion of, and preferably all, possible I/O addresses in a system. Further included are: an I/O decode map pointer adapted to point to a memory address where said I/O decode map is located; an I/O decode cache adapted to cache said decode information with respect to ones of I/O addresses of which accessing has been previously performed with respect to said I/O decode map; and an I/O snooper/storer adapted to snoop said I/O decode map with any I/O address to retrieve said decode information corresponding to said I/O address, and further adapted to store retrieved said decode information into said I/O decode cache. The I/O decode map can be located within at least one of system management memory (SMM) or basic input/output system (BIOS) memory space. Implementation can further be made in a computing system and method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.