Parallel redundancy encoding apparatus
US6336192B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 12, 1999 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Feb 12, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/14
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A channel-to-channel skew compensation apparatus is provided with N number of frame synchronization circuits 11 for generating frame signals to indicate data position of parallel data on a common time axis for each data transmission channel; a reference timing determination circuit 16 for determining a reference timing based on N frame signals output from the frame synchronization circuit 11; a skewing amount detection section 15 for generating N skewing amount signals according to the reference timing determined by the reference timing determination circuit 16; and a timing compensation section 13 for adjusting output timing of parallel data for each transmission channel according to the skewing amount signal generated by the skewing amount detection section 15.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.