Chip testing system
US6336198B1 · kind B1 · utility
0Cited by
3References
13Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Mar 26, 1999 |
| Grant date | Jan 1, 2002 |
| Priority date | — |
| Expiry date | Mar 26, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31926
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A chip testing system using an internal signal of the chip under test to produce a blanking signal so as to avoid a conflict in the turn-around cycle between input mode and output mode. The preceding signal, posterior signal and reverse phase signal of the output enable signal of the chip under test are used to match with a testing circuit for producing a blanking signal, which is driven only when the output enable signal is at a high potential, enabling the state machine in the chip to control data reading time, so as to avoid a conflict in the turn-around cycle between input mode and output mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.