Apparatus and method for doubling the frequency of a clock signal
US6337588B1 · kind B1 · utility
5Cited by
4References
18Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jul 17, 1998 |
| Grant date | Jan 8, 2002 |
| Priority date | — |
| Expiry date | Jul 17, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K5/00006
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A circuit for doubling the frequency of a periodic input signal includes an input stage to produce a first signal pulse during a first half of a first cycle of the periodic input signal and a second signal pulse during a second half of the first cycle of the periodic input signal. A reset stage produces a first reset signal that terminates the first signal pulse and a second reset signal that terminates the second signal pulse. The first signal pulse and the second signal pulse form a two cycle output signal during the first cycle of the periodic input signal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.