Data processing system and method to estimate power in mixed dynamic/static CMOS designs
US6338025B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 8, 1998 |
| Grant date | Jan 8, 2002 |
| Priority date | — |
| Expiry date | Oct 8, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/33
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An apparatus and method for determining power consumption in logic devices including mixed static and dynamic logic blocks is implemented. Input logical signals are tagged as having dynamical behavior or static behavior, and the power consumption of the logic block determined according to the behavior of the input signal. If an input signal has dynamic behavior, an output signal making a transition in response thereto will make two transitions per clock cycle, and the per cycle power consumption of the logic block is accordingly weighted. In another embodiment, a Boolean behavior signal is calculated for each block from clock phase tags and “one cycle per cycle” circuit level simulations. The per cycle power consumption of each logic block receives a weight in response to the Boolean behavior signal, according the behavior of the block characterized thereby.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.