Crash recovery without complete remirror
US6338126B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 6, 1999 |
| Grant date | Jan 8, 2002 |
| Priority date | — |
| Expiry date | Dec 6, 2019 |
Classification
- Technology area (CPC Y)Emerging Cross-Sectional Technologies
- CPC primaryY10S707/99955
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A primary computer system and a backup computer system each have an associated memory. For each write request, a copy of the request is forwarded to a delay buffer and memory queue associated with the primary computer system, and a copy is forwarded to a memory queue of the backup computer system. The backup computer system transmits an acknowledgement signal to the primary computer system when the backup computer system receives its copy of the request. The write request in the delay buffer of the primary computer system is executed in the primary memory only upon receipt of this acknowledgement signal. Thus, the backup computer system knows of every request executed in the primary memory. The write request is executed in the backup memory at any time after the backup computer system receives the write request. The write requests are deleted from the memory queues (primary and backup) when the associated computer system confirms that the write request was executed in the memory of the opposite computer system. Should the primary (or backup) computer system shut down, the requests are accumulated in the opposite backup (or primary) memory queue. When the primary (or backup) compute…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.