Method for manufacturing chip-scale package and manufacturing IC chip
US6338980B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 1, 2000 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | Aug 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/18162
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
In manufacturing a chip-scale package, a plurality of pads is formed in predetermined positions on an active face of an IC wafer, and projected electrodes are formed on the pads. Then, a groove is formed on the active face of the IC wafer along a line that the IC wafer is divided into individual pieces, and a protective resin is applied on the active face of the IC wafer including the groove. Thereafter, an adhesive member is applied on the active face on which the protective resin is applied, and an inactive face of the IC wafer which is fixed by the adhesive member is ground until the protective resin in the groove appears at the inactive face of the IC wafer. Then, the adhesive member applied to the active face is removed, and an adhesive member is applied to a ground face of the IC wafer, which has been ground in the grinding step. The protective resin is diced along the line into chip-scale packages in a state where the IC wafer is fixed by the adhesive member, and after that, the adhesive member applied to the ground face is removed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.