Method for fabricating self-aligned thin-film transistors to define a drain and source in a single photolithographic step
US6338988B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 30, 1999 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | Sep 30, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/674
Abstract
A method for forming a thin film transistor having source and drain electrodes self-aligned to a gate electrode by employing a single lithographic step includes forming an opaque gate electrode on a substrate, depositing a first dielectric layer on the gate electrode and the substrate, depositing a semiconductor layer on the first dielectric layer, and depositing a second dielectric layer on the semiconductor layer. A first photoresist is deposited on the second dielectric layer and patterned by employing the gate electrode as a mask for blocking light used to expose the first photoresist. The second dielectric layer is etched to form a top insulator portion of the second dielectric layer in alignment with the gate electrode. The first photoresist is removed. A doped semiconductor layer and a conductive layer are deposited. A second photoresist is formed on the conductive layer. The second photoresist is patterned to form components patterns and to form a contiguous transistor electrode pattern covering the top insulator portion. Non-selectively etching the second photoresist and the conductive layer, a gap is formed in the second photoresist for the transistor electrode pattern at…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.