Data I/O buffer control circuit
US6339343B1 · kind B1 · utility
8Cited by
14References
12Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Sep 28, 1999 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | Sep 28, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C11/4096
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A circuit controls data input/output buffers, where an input buffer is disabled during a read mode for reducing power consumption. In a preferred embodiment, a data input buffer is enabled in response to a control signal to receive data from an input/output pad. A data output buffer provides data to the input/output pad in response to the control signal. A data input/output buffer control unit generates the control signal to disable the data input buffer and enable the data output buffer in read mode. Preferably, the circuit is readily applicable to a memory device, such as a Synchronous Dynamic Random Access Memory (SDRAM).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.