Semiconductor storage apparatus having main bit line and sub bit line
US6339549B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 9, 2000 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | Feb 9, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/18
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
To provide a semiconductor storage apparatus capable of reducing a chip area, one main bit line is provided to a plurality of sub bit lines commonly connected with drains of memory cell transistors, the plurality of the bit lines are connected to ends on one side of switches at a first stage, control terminals of which are respectively inputted with column selecting signals and ends on other side of the switches are commonly connected and connected to the main bit line via a switch at a second stage, a control terminal of which is inputted with a column selecting signal, the sub bit lines are wired to a first wiring layer, the main bit line is wired to a second wiring layer and the second wiring layer is wired with power source lines, lines of voltage control signals in erasing or writing and high voltage power supply lines in regions among the main bit lines.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.