Semiconductor memory device
US6339556B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 14, 2000 |
| Grant date | Jan 15, 2002 |
| Priority date | — |
| Expiry date | Nov 14, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/28
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A semiconductor memory device having a plurality of cell arrays and one reference cell array according to the present invention includes a first current-to-voltage converting means that converts a cell current input from a cell array into a main cell voltage, a second current-to-voltage converting means that converts a reference cell current input from the reference cell array into a reference cell voltage, a global bit line that connects the first current-to-voltage converting means and the plurality of cell arrays, and a dummy global bit line that connects the second current-to-voltage converting means and the reference cell array, wherein the impedance of the global bit line is equal to the impedance of the dummy global bit line.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.