Automatic clock phase adjusting device and picture display employing the same
US6340993B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Sep 20, 1999 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Sep 20, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04N5/126
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
An automatic clock phase adjusting device is employed principally in a picture display to adjust automatically the phase of a clock signal given to an A/D converter which converts an analog image signal into a corresponding digital image signal. The automatic clock phase adjusting device comprises a delay circuit that delays the phase of the clock signal; an image level detecting circuit that detects the image level of a horizontal image starting portion of the digital image signal and the image level of an image terminating portion of the digital image signal; and a control circuit that controls a delay by which the delay circuit delays the clock signal on the basis of the output signal of the image level detecting circuit. The control circuit controls the phase delay by which the delay circuit delays the clock signal, combines the image level of the horizontal image starting portion of the digital image signal, and the image level of the horizontal image terminating portion of the digital image signal to obtain a combined image level on the basis of the output signal of the image level detecting circuit, and selects an optimum phase of the clock signal in which the combined image…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.