Method and system for testing a bit cell in a memory array
US6341091B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Nov 6, 2000 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Nov 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/04
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method for testing a cell in a device for reliability is disclosed. The cell us coupled to a reference voltage and a current source. The method and system comprises measuring a mirrored current through the device at first predetermined gate voltage and measuring a mirrored current through the device at a second predetermined voltage. The method and system includes determining the threshold voltage of the cell and heating the device for a predetermined period of time. Finally, the method and system includes calculating a new threshold voltage if the measured mirrored current is different from the previously measured current. Accordingly, a system and method in accordance with the present invention addresses this drift problem by testing the characteristics of the memory array on a bit by bit basis. A system and method in accordance with the present invention includes a mirrored current source arrangement. The mirrored current source arrangement allows for the determination of the overall change in characteristic of the threshold voltage. In so doing, the device can be tested more accurately and quickly, thereby reducing the time for testing and increasing the reliability of the de…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.