Method and apparatus for functional testing of memory related circuits

US6341094B1 · kind B1 · utility

Assignee

• LSI Logic Corporation · US

Inventor

• Stefan Auracher · Baierbrunn, DE

Key dates

• Filing date: Jul 30, 2001
• Grant date: Jan 22, 2002
• Expiry date: Jul 30, 2021

Classification

• Technology area (CPC G): Physics
• CPC primary: G11C29/56
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

An apparatus for testing a functional operation of a memory related circuit. The memory related circuit may be represented by a first circuit model defining a circuit under test. The apparatus may comprise a storage device and a processor. The storage device may be configured for storing the first circuit model representing the circuit under test, and for storing a second circuit model. The second circuit model may represent a testbench circuit for interfacing with the circuit under test, and may include a first memory and monitor circuitry. The first memory may be configured for interfacing with a first port of the circuit under test. The monitor circuitry may be configured for interfacing with the at least one of said memory and a second port of the circuit under test, for monitoring the response of the circuit under test as simulated signals are applied thereto. The processor may be configured for processing the first and second circuit models to simulate the response of the circuit under test when the simulated signals are applied thereto via the testbench circuit. The simulated signals may simulate read and write accesses to the circuit under test.