ATM node having local error correcting procedures
US6341132B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 4, 1998 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Feb 4, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L2012/5652
- WIPO fieldTelecommunications
- WIPO sectorElectrical engineering
Abstract
A telecommunication node for an Asynchronous Transfer Mode (ATM) telecommunication network performs Segmentation and Reassembly (SAR) of ATM cells. The SAR particularly provides Virtual Channel Identifier (VCI) and Virtual Path Identifier (VPI) translation and further provides a Direct Memory Access (DMA) for accessing an external storage. When the VCI and VPI identifiers are representative of an Error Code Correcting (ECC) procedure to be carried out in the local mode, the SAR circuit performs a first DMA access which is decoded by an address decoder. Conversely, when no ECC procedure is locally required, the SAR decodes the VCI and VPI and performs a second DMA access which is also decoded by the address decoder. The latter decoding is then used by a Reed-Solomon Coder and Decoder for possibly performing an error correcting procedure on the ATM message formed by the ATM cells being processed.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.