Automatic clock switcher
US6341355B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 16, 1999 |
| Grant date | Jan 22, 2002 |
| Priority date | — |
| Expiry date | Mar 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F1/08
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Upon receiving a normal select signal to switch from one clock to another the first clock continues as the output for a number of clock periods. The normal select signal is treated as a disconnect control signal only at the next positive edge of the first clock. The disconnect signal is delayed for a number of cycles and then applied to the control gate of the first clock only when a negative edge of the first clock is detected. Once the disconnect control signal has been issued and the first clock output is dead, the disconnect control signal starts the sequence for connecting the second clock to the output. The connect control signal is accepted at the next positive edge of the second clock, delaying the connect signal for a number of cycles and applying the connect signal to the control of the second clock only when a negative edge of the second clock is detected causing the second clock to disconnect from the output only at a negative edge. The failure of a specific clock is automatically detected by detecting a clock edge and counting clock periods of a second clock until detecting a second clock edge. Upon detecting the second edge before a predetermined number of second cloc…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.