Method of forming insulating spacers in DRAM chips
US6342450B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 30, 2000 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | Jun 30, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B12/038
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
There is disclosed an improved method of forming the spacer which isolates the gate conductor from the metal contact with the diffusion (source/drain) region of each array transfer transistor for all memory cells of a DRAM chip. According to the method there is provided a structure consisting of a silicon substrate having a diffusion region formed therein and gate conductor (GC) lines formed thereon. Then, an oxynitride layer and a silicon nitride (Si3N4) layer are conformally deposited in sequence onto the structure by LPCVD in the same tool for total clusterization. Next, the structure is anisotropically dry etched with a chemistry that is Si3N4/oxynitride selective to expose the oxynitride layer between the GC lines and the upper portion thereof in a one step process to form the Si3N4 spacers. Still in accordance with the invention, the above method finds a valuable application in the fabrication of borderless metal contacts in DRAM chips wherein the risk of having potential an electrical short between the gate conductor and the metal contact is substantially eliminated.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.