Duty cycle correction circuit of delay locked loop
US6342801B1 · kind B1 · utility
40Cited by
22References
8Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | Jun 29, 2000 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | Jun 29, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03L7/0812
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A duty cycle correction circuit of a delay locked loop circuit in a Rambus DRAM, decreasing a clock locking time by previously correcting a storage capacitor value to a setting value so as to provide a duty cycle correction within a short time in exiting a power save mode of delay locked loop, and accordingly, can realize a the power save mode capable of a high speed movement and without a time limit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.