Semiconductor memory device of shared sense amplifier system
US6343038B1 · kind B1 · utility
14Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Aug 31, 2000 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | Aug 31, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/14
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
In a semiconductor memory device including a bit line precharge/equalizing circuit, the control system of the bit line precharge/equalizing circuit is changed in the normal operation mode and in the test mode. In the test mode, the bit line precharge/equalizing circuit is temporarily turned ON when an internal activation signal becomes non-active and then the bit line precharge/equalizing circuit is turned OFF after the potentials of paired bit lines are completely equalized.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.