Fully synchronous pipelined RAM
US6343047B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 25, 2000 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | Jul 25, 2020 |
Classification
- Technology area (CPC —)General
Abstract
A memory system includes a memory, an input circuit and a logic circuit. The input circuit is coupled to receive a memory address and, during a write operation, the corresponding write data to be written into the SRAM. The logic circuit causes the write data to be stored in the input circuit for the duration of any sequential read operations immediately following the write operation and then to be read into the memory during subsequent write operation. During the read operation, data which is stored in the write data storage registers prior to being read into the memory can be read out from the memory system should the address of one or more read operations equal the address of the data to be written into the memory while temporarily stored in the write data storage registers. Thus, no “bus turnaround” down time is experienced by the system thereby increasing the bandwidth of the system. The system can operate in a single pipeline mode or a dual pipeline mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.