High speed one's complement adder
US6343306B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | May 18, 1999 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | May 18, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/3836
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A one's complement adder uses two two's complement adders, both of which are coupled to receive first and second addends at their addend inputs, however the first two's complement adder is adapted to output a first sum that is the one's complement sum that would result if no carry occurred upon addition of the first and second addends and the second two's complement adder is adapted to output a second sum that is the one's complement sum that would result if a carry did occur. A selector selects one of the first sum and the second sum as its output (and the output of the one's complement adder) based on whether or not a carry occurred. The indication of whether or not a carry occurred or not can be determined from the carry output of the first complement adder, with the first sum effected by setting the carry input for the first two's complement adder to “0” (no carry in) and the second sum effected by setting the carry input for the second two's complement adder to “1” (carry in). The selector can be a multiplexer with a select input coupled to the carry output of the first two's complement adder.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.