Cache blocking of specific data to secondary cache with a first and a second OR circuit
US6343345B1 · kind B1 · utility
23Cited by
116References
10Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 13, 2000 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | Jul 13, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0888
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A cache blocking mechanism ensures that transient data is not stored in a secondary cache of a router by managing a designated set of buffers in a main memory of the router. The mechanism defines a window of virtual addresses that map to predetermined physical memory addresses associated with the set of buffers; in the illustrative embodiment, only transient data may be stored in these buffers. The mechanism further blocks write requests directed to these predetermined memory buffers from propagating to the secondary cache, thereby precluding storage of transient data in the cache.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.