Methods and apparatus for dynamic instruction controlled reconfiguration register file with extended precision
US6343356B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 9, 1998 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | Oct 9, 2018 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/3016
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A reconfigurable register file integrated in an instruction set architecture capable of extended precision operations, and also capable of parallel operation on lower precision data is described. A register file is composed of two separate files with each half containing half as many registers as the original. The halves are designated even or odd by virtue of the register addresses which they contain. Single width and double width operands are optimally supported without increasing the register file size and without increasing the number of register file ports. Separate extended registers are also employed to provide extended precision for operations such as multiply-accumulate operations.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.