Executing multiple debug instructions
US6343358B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 19, 1999 |
| Grant date | Jan 29, 2002 |
| Priority date | — |
| Expiry date | May 19, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/318566
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
Apparatus for processing data is provided, said apparatus comprising: a main processor 4; an instruction transfer register ITR for holding a data processing instruction and accessible via a first serial scan chain SC4; a data transfer register DTR for holding a data value and accessible via a second serial scan chain SC5; debug logic 6, 12 for controlling said main processor 4, said instruction transfer register ITR and said data transfer register DTR such that a data processing instruction held within said instruction transfer register ITR is passed a plurality of times to said main processor 4 for execution upon a sequence of data values scanned into or from said data transfer register via said second serial scan chain. In this way operational speed of the debug mode is increased since the data processing instruction only needs to be transferred once.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.