Redundancy circuits for integrated circuit memory devices including repair controlling circuits and enable controlling circuits
US6345003B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jul 9, 1999 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Jul 9, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/80
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Integrated circuit memory device redundancy circuits include a plurality of field effect transistors and fuses, a respective field effect transistor and a respective fuse being serially coupled between a respective address line and a logic circuit to generate a selection signal for a redundant memory cell in response to a predetermined address on the address lines. A pump-up circuit generates a pump-up voltage from a power supply voltage, wherein the pump-up voltage is greater than the power supply voltage. The pump-up voltage is applied to the gates of the field effect transistors to activate the redundancy circuit. According to another aspect, a redundancy circuit for an integrated circuit memory device comprises a repair controlling circuit that includes a repair fuse and that generates a repair control signal in response to opening of the repair control fuse. The enable controlling circuit is responsive to the repair controlling circuit and includes an enable fuse to generate a redundant enable signal in response to the repair control signal and opening of the enable fuse. A redundancy signal generator is responsive to the enable controlling circuit to generate a selection sign…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.