Defective memory block handling system by addressing a group of memory blocks for erasure and changing the content therewith
US6345367B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Feb 16, 1999 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Feb 16, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/16
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A fault tolerant memory system includes an array of block-erasable storage elements (12). Each block (12) of storage locations is sub-divided into sub-groups (14) of storage elements. A control information store means holds defect information for each group in each block and an address counter holds the addresses of the groups in the particular erase block being erased. A testing circuit checks whether the defect information stored in the control information store for the particular group currently addressed by the address counter indicates that the particular group contains one or more defective storage locations. If it does it increments the address counter.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.