System and method for testing high speed VLSI devices using slower testers
US6345373B1 · kind B1 · utility
82Cited by
8References
7Claims
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Key dates
| Filing date | Apr 22, 1999 |
| Grant date | Feb 5, 2002 |
| Priority date | — |
| Expiry date | Apr 22, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/31908
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
At-speed strategies for testing high speed designs on slower testers. At-speed testing schemes is provided that integrates the tester's speed limitations with the test generation process. Due to constraints placed at the test generation process, these schemes might result in a reduced fault coverage. To increase the fault coverage and reduce the test application time, the slow-fast-slow and at-speed strategies can be combined for testing high speed designs on slower testers. A slow tester that uses test vectors that are generated while taking into account the speed of the tester.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.