High voltage input buffer made by a low voltage process and having a self-adjusting trigger point
US6346829B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Aug 9, 2000 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | Aug 9, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03K19/018585
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A high performance high input voltage input buffer manufacture using a low voltage process contains an input buffer circuit (136) and a level shifter (132). The input buffer (136) will receive an input signal via a chip pad (112). The input signal from trip pad (112) will be provided to an inverter stack (135) that contains or is coupled to protection transistors (116, 114, 110, and 111). The protection transistors are biased by a reference generator (134) which outputs a voltage that is a function of the maximal voltage that can be provided on the chip pad (112). By using the circuit (134), the trigger point of the inverter stack (135) can be dynamically adjusted for any OVDD (110) value whereby input buffer performance is improved and made more flexible.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.