Variable delay path circuit
US6346842B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 12, 1997 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | Dec 12, 2017 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH05K2203/173
- WIPO fieldAudio-visual technology
- WIPO sectorElectrical engineering
Abstract
A variable delay path circuit having delay paths of different lengths is disclosed. Any of the delay paths can be selected to match the operating conditions of the system. In one embodiment of the invention, a delay path circuit having two delay paths connects a driver and receiver. Each of the two delay paths contains sites at both ends for placing zero ohm resistors, solder or copper slugs. To select one of the two delay paths, zero ohm resistors, solder or copper slugs are placed in the sites at the ends of the desired delay path. The delay is then dictated by the time it takes for a clocking signal to travel the length of selected delay path.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.