Method of operating flash memory
US6347054B1 · kind B1 · utility
10Cited by
18References
21Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 1, 2000 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | Feb 1, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
Abstract
A method of erasing electrically a programmable memory cell which cell includes a transistor formed in a region of semiconductor material. The transistor has a source region, a drain region, a floating gate, and a control gate. The method includes lowering the control gate to a potential no more negative than 6.5 volts, disconnecting the source and drain regions from any potential source, and placing the region of semiconductor material at a potential no more positive than 8.0 volts.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.