Recording of result information in a built-in self-test circuit and method therefor
US6347056B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 16, 2001 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | May 16, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C29/44
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An integrated circuit has a Built-In Self-Test (BIST) controller (10) that has a sequencer (16) that provides test algorithm information for multiple memories (44, 46, 48, 50). The sequencer identifies the test algorithm that is to be performed and multiple memory interfaces (32, 34, 36, 38) interpret the output of the sequencer and perform the algorithm on the multiple memories. The multiple memories may be different or the same regarding type, size, data widths, etc. Having multiple memory interfaces provides flexibility to tailor the test algorithm for each memory, but yet keeps the advantage of a single source of identifying the test algorithm. With the memories being non-volatile, timing information with regard to the test algorithm is stored in the memories. When test algorithms fail or complete execution, pertinent BIST information is stored in non-user addressable space of the multiple memories.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.