Data bus structure for use with multiple memory storage and driver receiver technologies and a method of operating such structures
US6347367B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 29, 1999 |
| Grant date | Feb 12, 2002 |
| Priority date | — |
| Expiry date | Jan 29, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F13/4239
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The disclosed invention relates generally to electronic data storage systems that access data storage memory modules via a data bus comprised of multiple data query lines and, more particularly, to an electronic data storage system provided with a data bus that can be selectively provided with terminations thereby permitting the data storage memory to use either modules that require that the data query lines be open-ended, i.e., without terminations or modules that require that the data bus be terminated and to a method for operating such a system. The present invention is particularly directed to a single memory system that can accommodate either 3.3V DIMMs or DDR DIMMs. This is especially accomplished by providing the processor circuit, used in memory storage systems, with both (3.3V) receiver/driver circuits and double rate (DDR) receiver/driver circuits, with an identification circuit for identifying the type of DIMMs in the memory system coupled thereto, a selection circuit for selecting the receiver/driver circuits required to access the identified DIMMs, and switch for adding or removing terminations to the data query lines, interconnecting the selected receiver driver circu…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.