Method and apparatus for assigning pins for electrical testing of printed circuit boards
US6348805B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 10, 1999 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Mar 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG01R31/2886
- WIPO fieldMeasurement
- WIPO sectorInstruments
Abstract
A process for creating a pin assignment for a test fixture for electronic circuits is disclosed. A difficulty rating is determined for each test point on an electronic circuit. The difficult areas are assigned the pins on a test grid, with the difficulty rating of adjacent test points being iteratively determined as the process continues. If a pin cannot be assigned because of conflicts, one or more adjacent test points are reassigned pins, with the difficulty matrix being recalculated with each change and with pins being reassessed and reassigned. When all test points are assigned a pin, the pins are checked to see if they interfere with each other, and further iterations may result.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.