Linearization of FET channel impedance for small signal applications
US6348834B1 · kind B1 · utility
6Cited by
2References
3Claims
0Family size
Assignee
Inventor
Key dates
| Filing date | May 15, 2000 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | May 15, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH03F1/301
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A system that provides a means of effectively applying a mathematical substitution to the characteristic V/I equation for FET devices operating in the ohmic region that causes the non-linear (distortion producing) term to be cancelled thereby improving the realizable channel impedance linearity by orders of magnitude. The system comprised of a means to sum an isolated specific portion of the information signal applied to the FET with the Gate controlling voltage to produce a signal value that achieves the improved linearity result when applied to the FET Gate terminal.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.