5-ary receiver utilizing common mode insensitive differential offset comparator
US6348882B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 25, 2000 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Jul 25, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0274
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A signal converter is provided for converting multiple level encoded digital signals into a binary equivalent signal. The signal converter includes a reference voltage generator, a plurality of four-input differential comparators, timing recovery circuitry, and signal conversion circuitry. The reference voltage generator is operative to generate a plurality of progressively larger differential reference voltages. The plurality of differential comparators are each operative to compare magnitude of a differential input voltage with magnitude of a dedicated one of the progressively larger differential reference voltages and produce a differential output voltage having a first logical sense if the magnitude of the differential input voltage is greater than the magnitude of the differential reference voltage, and having a second logical sense if the magnitude of the differential input voltage is less than the magnitude of the differential reference voltage. Each comparator has an offset input voltage. The timing recovery circuitry is configured to receive the differential output voltages from each of the differential comparators and is operative to derive a clock via edge detection and …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.