High speed low power content addressable memory
US6349049B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2001 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Mar 22, 2021 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C15/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
One or more boost circuits are included within each row of CAM cells to increase the charging rate of its match line during match conditions. The CAM cells in each row control corresponding match transistors connected in series between a supply voltage and a match line. The match transistors collectively form a NAND match circuit. A boost circuit connected between a supply voltage and ground potential is coupled to a midpoint of the NAND match transistor chain. During compare operations, if all CAM cells match, all match transistors turn on and pull the match line toward the supply voltage. As the voltage at the midpoint of the match line reaches a threshold voltage, the boost circuit provides an additional charging path to more quickly charge the match line. If any CAM cell mismatches, its match transistor turns off and isolates the match line from the supply voltage.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.