Digital channelizer having efficient architecture for cyclic shifting and method of operation thereof
US6349118B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 1999 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Feb 26, 2019 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L5/06
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
The invention is a digital channelizer and a process for dividing an input bandwidth into at least some of N channels. A digital channelizer which divides an input bandwidth into at least some of N channels in accordance with the invention includes a window presum (102); a cyclic shift (24′), coupled to the I output groups of date words, having I cyclic shift paths, each cyclic shift path being responsive to a different output group of data words to produce I output groups of data words, each cyclic shift path comprising a plurality of word shifting elements each responsive to a group of data words; and a discrete Fourier transform (26′) coupled to the I output groups of cyclically shifted data words outputted from the cyclic shift.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.