Arithmetic processor for finite field and module integer arithmetic operations
US6349318B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Oct 14, 1999 |
| Grant date | Feb 19, 2002 |
| Priority date | — |
| Expiry date | Oct 14, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F2207/382
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
The present disclosure provides an arithmetic processor having an arithmetic logic unit having a plurality of arithmetic circuits each for performing a group of associated arithmetic operations, such as finite field operations, or modular integer operations. The arithmetic logic unit has an operand input data bus, for receiving operand data thereon and a result data output bus for returning the results of the arithmetic operations thereon. A register file is coupled to the operand data bus and the result data bus. The register file is shared by the plurality of arithmetic circuits. Further a controller is coupled to the ALU and the register file, the controller selecting one of the plurality of arithmetic circuits in response to a mode control signal requesting an arithmetic operation and for controlling data access between the register file and the ALU and whereby the register file is shared by the arithmetic circuits.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.