Electronic device package, and method
US6350954B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 24, 2000 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Jan 24, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/16195
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
An electronic package (100) has a semiconductor device (130), a two-layer (110, 120) printed circuit substrate (101), and a lead (140) for providing external connections for the package assembly (100). The first layer (110) has an electrical conducting surface structure (112); and the second layer (120) has a recess (125) to receive the device (130). The device frontside (131) is electrically coupled to the conducting surface structure (112) of the first layer (110) in a flip-chip arrangement. The backside (132) of the device (130) is coplanar to the surface (112) of the second layer (120). The lead (140) at least partially overlays the surface (122) of the second layer (120).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.