Linear capacitor structure in a CMOS process

US6351020B1 · kind B1 · utility

Assignee

• Motorola, Inc. · US

Inventors

• Marc Tarabbia · Austin, US
• Joseph Chan · San Francisco, US
• Geoffrey B. Hall · Austin, US

Key dates

• Filing date: Nov 12, 1999
• Grant date: Feb 26, 2002
• Expiry date: Nov 12, 2019

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/212

Abstract

A cumulative capacitor structure with desirably constant capacitance characteristics is disclosed. In one embodiment, the cumulative capacitor includes a set of four capacitors coupled in parallel between first and second terminals of the cumulative capacitor. In one embodiment, the first capacitor is comprised of a top plate formed of an n-type polysilicon coupled to the first terminal, a bottom plate comprised of a first accumulation/depletion region such as an n-well region coupled to the second terminal, and a first dielectric region between its top and bottom plates. The second capacitor has an n-type polysilicon terminal top plate coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and a dielectric between its top and bottom plate. A third capacitor has a p-type polysilicon top plate coupled to the first terminal, an accumulation/depletion region bottom plate coupled to the second terminal, and a third dielectric region between its top and bottom plates. The fourth capacitor has a p-type polysilicon terminal coupled to the second terminal, an accumulation/depletion region bottom plate coupled to the first terminal, and …