Zero-DC-power active termination with CMOS overshoot and undershoot clamps
US6351138B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Mar 22, 2001 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Mar 22, 2021 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/0298
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
An active terminating circuit has n-channel and p-channel sensing transistors with gates connected to a transmission line. The sensing transistors drive a back node connected to a pair of capacitors. One capacitor drives a p-gate node coupled to a gate of a p-channel clamping transistor, while the other capacitor drives an n-gate node coupled to a gate of an n-channel clamping transistor. The drains of the clamping transistors are connected to the transmission line. Resistors pull the p-gate node to the power-supply voltage and pull the n-gate node to ground when no transitions occur on the transmission line to achieve zero standby power. When a transition is detected, it is inverted and coupled through the capacitors to the p-gate and n-gate nodes. The p-channel clamping transistor is turned on for rising transitions, while the n-channel clamping transistor is turned on for falling transitions. Limiting transistors limit gate-node swings.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.