Direct digital synthesis pixel clock generator
US6351277B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 6, 2000 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Oct 6, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06K15/1219
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A Direct Digital Synthesis pixel clock generator for use in electrophotographic printers. A controller receives a start-of-scan signal and a facet 0 signal. In response, the controller sends a pre-stored frequency control word to a Direct Digital Synthesis Oscillator. The Direct Digital Synthesis Oscillator sends pulses at a frequency that depends on the frequency control word to a Digital Phase Shift Circuit. The controller also applies a sequence of delay profile words to the Digital Phase Shift Circuit. Each delay profile word causes the Digital Phase Shift Circuit to delay a contemporaneous pulse from the Direct Digital Synthesis Oscillator between 0° and 360° degrees, with the actual delay depending upon the delay profile word. The delay profile words are selected such that scan line pixels are “adjusted” in position. A phase-locked-loop circuit integrates and smoothes the frequency step changes. The output of the phase-locked loop circuit is applied to a synchronizer that synchronizes the pixel clocks with the start-of-scan. Alternatively, the controller applies a sequence of frequency profile words to a Direct Digital Synthesis Oscillator. The Direct Digi…
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.