Apparatus and method for providing direct current balanced code
US6351501B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 29, 1998 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Jun 29, 2018 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/4915
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A highly efficient bit encoder and a method related thereto are provided. The bit encoder transmit DC-balanced digital signals over a transmission line. To provide a DC-balanced signal, an input word's single-word disparity (SWD) value is compared to a running word disparity (RWD) value retrieved from a memory register. The RWD value indicates the cumulative DC-imbalance on the transmission line. If the disparity relationship of the SWD and the RWD satisfy a set of predefined rules, the input word is inverted to thereby offset the RWD. An inversion bit is appended to the digital input word to provide an output digital word to indicate to a receiver whether the transmitted output word is inverted to thereby permit recovery of the original system word. In one application, the DC-balanced signal transmits alternately control words and data words. A clock signal is transmitted on a separate clock transmission line to provide a clock signal for timing purposes and an embedded control signal indicating control or data mode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.