Data processor and data processing system
US6351788B1 · kind B1 · utility
Assignees
Inventors
Key dates
| Filing date | Jun 10, 1999 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Jun 10, 2019 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/0864
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A data processor including a central processing unit and a plurality of direct map cache memories (3, 4) has a plurality of area designating circuits (5, 6) for variably designating location and size of address area in the memory space managed the central processing unit and partially overlaps the address area designated by a plurality of area designating circuits. Thereby, the overlapped area (Eco) has a function as the 2-way set associative cache memory in combination with a plurality of cache memories. For the non-overlapping area, respective cache memory functions as the direct map cache memory. It is previously judged to attain the necessary data processing capability by arranging which processing routine to which address area and then executing such routine with what processing speed. Thereby, when cache object area is assigned to a plurality of cache memory, a plurality of cache memories are combined as a set associative cache for operation to the task which particularly requires high speed operation or to the data. As a result, the system can be optimized by improving the cache hit rate of the necessary area.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.