Risc processor using register codes for expanded instruction set
US6351806B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Oct 5, 2000 |
| Grant date | Feb 26, 2002 |
| Priority date | — |
| Expiry date | Oct 5, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F9/30185
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A RISC processor using a fixed length standard instruction word (32-bit) consisting of a fixed-length (6-bit) operation code and two register fields, uses one of the register fields to give certain operation codes multiple meanings. For most operations, the register codes refer to general purpose registers as such. However, for certain operations, including move and add, register codes 30 and 31 in the source register code field of the instruction word indicate that the next instruction word contains immediate data for that operation instead of the operand being located in the specified register itself. Further, for load, store and jump operations, the source register codes 30 and 31 in the source register code field indicates that those registers are to be used as base or index registers for indexed addressing, with an offset in the following instruction word added to the general purpose register 30 or 31 contents to form the address. And, for load and store operations, register codes 24 through 27 in the source register field indicate various forms of byte (8-bit) or half-word (16-bit) memory transfers instead of a word (32-bit) transfer. All other register codes indicate normal …
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.