Method of forming DRAM cell arrangement

US6352894B1 · kind B1 · utility

Assignee

• Siemens Aktiengesellschaft · DE

Inventors

• Bernd Goebel · Dresden, DE
• Wolfgang Roesner · Austin, US
• Franz Hofmann · Munich, DE
• Emmerich Bertagnolli · Munich, DE
• Eve Marie Martin · Munich, DE

Key dates

• Filing date: Jan 13, 2000
• Grant date: Mar 5, 2002
• Expiry date: Jan 13, 2020

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y10S438/947

Abstract

A storage cell has a number of projections of a semiconductor substrate arranged in rows and columns, neighboring rows of the projections being translation-symmetrical in relation to a y-axis which extends parallel to the columns. Each of the projections has at least one first source/drain region of a selection transistor and one channel region arranged below the first source/drain region, which is surrounded by a gate electrode annularly. A storage capacitor is connected between the first source/drain region and a bit line. The bit line as well as the storage capacitor are arranged essentially above the semiconductor substrate. Second source/drain regions of selection transistors are buried in the semiconductor substrate and connected with each other. Word lines can be formed self-justified in the form of adjacent gate electrodes. The projections can be created by etching with only one mask. The storage cell can be produced with an area of 4F2, F being the minimal structural size that can be produced in the respective technology.