ISI-rejecting differential receiver
US6353343B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 26, 2000 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Jun 26, 2020 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH04L25/03878
- WIPO fieldDigital communication
- WIPO sectorElectrical engineering
Abstract
A digital differential receiver IC that rejects the inter-symbol interference (ISI) that is imposed upon differential digital signals when long runs of a digital state (0 or 1) are transmitted over long cables. The ISI-rejecting differential receiver IC is implemented in either bipolar technology (n-p-n or p-n-p) or in insulated gate FET technology (p-channel or n-channel). The primary differential pair of transistors is connected to a secondary differential pair of transistors through a filter network so that a high pass “shelf” filter transfer function exists between the differential input signals and the output signals. This transfer function mitigates ISI by reducing the gain for long runs of a digital state (low frequencies) and enhancing the gain for the state transition edges (high frequencies).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.