Semiconductor memory device having pipe register operating at high speed
US6353574B1 · kind B1 · utility
Assignee
Inventor
Key dates
| Filing date | Jun 28, 2000 |
| Grant date | Mar 5, 2002 |
| Priority date | — |
| Expiry date | Jun 28, 2020 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C7/1051
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A pipe register for use in a semiconductor memory device, wherein said semiconductor memory device includes global input/output (I/O) lines, complementary global I/O lines, and pipe registers, coupled to said global I/O lines and said complementary global I/O lines, for detecting the data loaded on said global I/O lines and complementary global I/O lines to store the data, includes: a data detecting unit, coupled to said global I/O lines and complementary global I/O lines, for detecting whether the data is loaded on said global I/O lines and complementary global I/O lines; a control signal generating unit for sensing edges of the data loaded on the global I/O line and the complementary global I/O line to generate a rising edge sensing signal and a falling edge sensing signal; and a plurality of storage units for storing the data loaded on said global I/O lines and said complementary global I/O lines in response to a reset signal, the falling edge sensing signal and the rising edge sensing signal and for outputting the data in response to the pipe counter signal outputted from said pipe counting unit.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.